Synopsys and Singapore's Agency for Science, Technology and Research have signed a memorandum of understanding on semiconductor packaging and simulation technologies.
The agreement focuses on advanced packaging and chiplet-based architectures through A*STAR's Institute of Microelectronics.
The collaboration will run through the A*STAR IME-Ansys Joint Innovation Consortium for Semiconductor Excellence, or JICSE. The consortium brings together A*STAR's Institute of Microelectronics and Ansys, now part of Synopsys, as a platform for joint research and development in advanced system-in-package technologies.
At its core is a push to use digital modelling and analysis earlier in semiconductor development. As packages grow more complex, chipmakers and electronics companies are trying to identify design, reliability and performance issues before building physical prototypes, with the aim of reducing development time and manufacturing risk.
That shift is making packaging a more strategic part of the semiconductor supply chain. While chip design has long drawn most of the industry's attention, advanced packaging is becoming more important as companies seek to improve computing performance, manage power and integrate multiple functions into smaller systems.
Chiplet-based designs are part of that shift. Instead of building all functions onto a single large chip, manufacturers can combine several smaller dies in one package. The method is increasingly used in artificial intelligence and high-performance computing systems, where performance, yield and cost all matter.
Consortium focus
JICSE's initial phase will focus on mechanical design, modelling and analysis. Areas of work include package and wafer warpage, thermo-mechanical stress, solder joint reliability and moisture-induced failures in multi-chiplet architectures.
These issues are central to whether advanced semiconductor products can be manufactured at scale. Warpage can affect assembly and alignment, thermal stress can shorten product life, and solder joint failures remain a common reliability concern as packages become denser and more complex.
Moreover, the consortium will explore research projects with academic institutions and offer technical training programmes and seminars for industry participants. A*STAR IME will lead consortium-based research and development, drawing on its expertise in advanced packaging and applied research.
Synopsys will support adoption of simulation-led design methods by providing trial licences for its Ansys simulation software to A*STAR IME and up to 10 consortium member companies. The arrangement suggests the partners want to broaden access to modelling tools among local companies, not just large multinational groups with established in-house simulation resources.
Singapore role
The deal also reflects Singapore's effort to strengthen its position in semiconductors beyond fabrication and assembly. The city-state has long hosted manufacturing and test operations for global chip groups, but policymakers and public research bodies have increasingly sought to deepen local expertise in higher-value areas including design, packaging and process development.
A*STAR has played a central role in that strategy by linking public research institutes with industry projects. Its Institute of Microelectronics has been involved in packaging, sensors and materials research, often working with commercial partners on technologies that can move into production settings.
For Synopsys, the agreement offers access to a research and industry network focused on packaging challenges at a time when design software groups are trying to expand beyond traditional electronic design automation. Simulation tools used for thermal, structural and reliability analysis are becoming more relevant as semiconductor and systems engineering increasingly overlap.
Terence Gan, Executive Director, A*STAR IME, set out the institute's view of the partnership.
"Advanced packaging is fast becoming a critical differentiator in global semiconductor innovation, particularly as systems grow more complex and AI-driven. Through this collaboration with Synopsys, A*STAR IME is combining our R&D expertise with Synopsys' line of Ansys simulation technologies to co-develop next-generation semiconductor packaging and simulation technologies. This enables companies to innovate with greater speed and confidence, and reinforces Singapore's position as a leading hub for semiconductor innovation," Gan said.
His comments implicate a broader industry trend in which packaging is no longer treated solely as a back-end manufacturing task. Instead, it is becoming a design consideration from the earliest development stages, particularly for processors and systems aimed at artificial intelligence workloads.
Synopsys also framed the work as part of a wider move towards system-level design and modelling.
"The future of semiconductor innovation is going to be increasingly defined by how effectively complex systems are designed and integrated. Through this collaboration with A*STAR IME and the launch of JICSE, Synopsys is committed to empowering an industry-wide shift toward simulation-led, system-driven design. This collaboration aims to back local companies in Singapore for tackling key challenges in reliability, performance, and scalability - while also fast-tracking the time-to-market for next-generation AI and HPC technologies," said Moon.
The agreement leaves open how many companies will ultimately join the consortium, but the initial software access for up to 10 members gives the initiative an early framework as Singapore seeks to build deeper semiconductor expertise in advanced packaging.