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Arm expands Arteris security tools across CPU portfolio

Arm expands Arteris security tools across CPU portfolio

Fri, 17th Jul 2026 (Today)
Sean Mitchell
SEAN MITCHELL Publisher

Arteris has expanded its partnership with Arm to extend hardware security assurance tools across Arm's CPU IP portfolio, following five years of collaboration.

Arm engineering teams are broadening their use of Arteris' Cycuity Radix product after deploying it on selected CPU designs. The technology is now being added to more next-generation processor programmes as Arm works to identify and mitigate potential security weaknesses during development.

The agreement deepens a relationship centred on processor security at a time when chipmakers face greater scrutiny over the resilience of the hardware underpinning artificial intelligence systems, cloud infrastructure and connected devices. Security assurance in semiconductor design has become more prominent because vulnerabilities in low-level architecture can be difficult and costly to address once products are in use.

Under the arrangement, Arm will continue integrating Cycuity Radix into its CPU design security assurance processes. The tool provides visibility into design relationships and potential attack surfaces, helping engineers identify issues earlier in the development cycle.

Design flow

The process begins with architectural and micro-architectural security risk assessments. These identify critical assets and test them against known threat models to set security objectives for each design.

Arm applies the methodology during the CPU design flow rather than as a post-silicon audit. The approach is intended to surface security issues before chips reach production, when fixes are typically more disruptive and expensive.

Automation and the reuse of security properties across CPU projects also help Arm scale the verification process across multiple designs. That is particularly relevant across a broad CPU portfolio, where common elements recur across product generations.

The partnership centres on trusted compute, which both companies described as important for AI systems running in data centres and at the edge. Processor security has become a growing concern as AI workloads spread across more infrastructure and devices, increasing the number of systems exposed to attack.

In a comment included with the announcement, Arm linked the work to confidence in deploying compute across different environments. "Trusted compute is foundational to the next generation of AI, from agentic AI infrastructure in the data center to intelligent systems at the edge. Through our work with Arteris, we are strengthening our security assurance processes across our CPU portfolio, helping ensure developers can deploy secure, high-performance, energy-efficient compute with greater confidence from cloud to edge," said Lyndon Fawcett, Head of Product Security at Arm.

Security focus

For Arteris, the expanded use of Cycuity Radix provides a high-profile customer reference for its hardware security assurance business. The company is better known for network-on-chip interconnect intellectual property and system-on-chip software used in semiconductor design.

It also highlights semiconductor cybersecurity as a growing part of the broader effort to secure electronic systems. That reflects a wider industry shift as security considerations move closer to the start of the chip design process instead of being addressed chiefly through software mitigations after deployment.

"Semiconductor cybersecurity is rapidly becoming a critical part of securing all our electronic systems, including AI data centers," said K. Charles Janac, President and Chief Executive Officer at Arteris. "Arm is leading the way in secure compute by making security a core requirement across every CPU it ships. Leveraging Arteris technology, Arm is building more rigorous security assurance into CPU development at every level."

The expanded partnership indicates that hardware-level security verification is becoming more embedded in mainstream CPU development. It also shows how chip designers are seeking repeatable methods to assess threats across successive architectures rather than limiting reviews to selected products.

Arm's decision to broaden adoption across additional processor programmes suggests the earlier deployment on selected designs delivered enough value to justify a wider rollout. The companies did not disclose financial terms.

The methodology is intended to expose potential weaknesses early so they can be fixed in design rather than mitigated after delivery.